1. Field of the Invention
The present invention relates to a method for analyzing process parameters, and more particularly, to a method for analyzing in-line quality control (QC) test parameters.
2. Description of the Prior Art
In a semiconductor manufacturing technique, many processes, such as the photolithography processes, the etching processes, and the ion implantation processes are required to complete the fabrication of a semiconductor product. That means a large number of equipments and complicated procedures are utilized in a semiconductor manufacturing process. Therefore, those of ordinary skill in the art are concentrated on ensuring the proper operation of equipments, sustaining or improving production yields, detecting and verifying problems, and periodically maintaining facilities for production, etc, so as to maintain the company's operation in good progress and produce products having good quality.
In order to identify the semiconductor processing problems, the following data, such as the process parameter data, the in-line QC test data, the defect inspection data, the sample test data, the wafer test data, and the final test data, are analyzed. The in-line QC test data refers to the data obtained from QC tests of the wafer in process, and the QC tests are usually executed after certain process steps.
FIG. 1 is a flow chart of a prior art method for analyzing in-line QC test parameters. As shown in FIG. 1, a step 101 is first executed to do tests of an in-line QC test item, such as a film-thickness test, to each wafer. A step 102 is thereafter executed to observe the results of the in-line QC test item of each wafer, so as to find out the products having abnormal in-line QC test results. Normally, the in-line QC test item to be observed is the process item executed in the last process step.
Those skilled in the art then performs a step 103 to use personal experience and the in-line QC test parameters of the abnormal products found from the step 102 to determine the possibly faulty process step, such as the thermal oxidation equipment, the silicon nitride deposition equipment, the polysilicon deposition equipment, etc.
Finally, a step 104 is used to check the various equipments used in the possibly faulty process step that is determined in the step 103, so as to find out the ill-functioned equipment. For example, when the thickness of the silicon nitride layer is found abnormal, the faulty process step is determined to be the deposition step of the silicon nitride layer, and the ill-functioned equipment is possible to be the deposition equipment, the etching equipment, etc.
Referring to FIG. 2 of a flow chart of another prior art method for analyzing in-line QC testparameters, in-line QC test results are used to predict the yield of the subsequent process to improve utility of the semi-finished products. At the beginning of the method, a step 201 is performed to execute tests of anin-line QC test item to each wafer, such as a film-thickness test. Following that, a step 202 is performed to observe the results of the in-line QC test item of each wafer to find out the products having abnormal in-line QC test results.
When the in-line QC test item of the products is found abnormal, two methods are typically used: one is shown as a step 203, abandoning the lot of products as failed products; the other is shown as a step 204, predicting whether the lot of products can pass the following sample test or wafer test or not, if the predicting answer is no, perform the step 203, and if the predicting answer is yes, perform a step 205 to keep the lot of products to continue the following processes and tests.
The prior methods use personal experience to determine analyzing results (such as in the step 103) or predict the following test results of the products (such as in the step 204), resulting in the accuracy and the reliability of the analyzing results doubtful. Furthermore, the human affairs in semiconductor manufacturing change frequently. Engineer's personal experience is difficult to transfer. The capacity of each engineer is limited, meaning the engineer is unable to look after the operation status of all of the equipment. When the test results of the semiconductor products indicate abnormalities, it is thus difficult for engineers, lacking in experience, to judge which point causes the problem to occur. Therefore, a lot of time is consumed to do related research, and even worse, wrong decisions are made. This will not only reduce the efficiency of processes, but also increase the cost. Furthermore, the in-line production status cannot be improved in time to increase the production yield.
It is therefore very important to provide an analyticalmethod to rapidly and correctly judge which point causes the problem to occur when the in-line QC test results of semiconductor products indicate abnormalities.